EOS Protection Circuit for USB2 Transceiver

This paper presents CMOS integrated electrical over stress (EOS) protection circuit for USB2 transceiver. A unique full speed SE0 state in USB2 standard protocol produces overshoot and undershoots in presence of on board choke. The purpose of choke is to minimize EMI for USB2 differential signalling. This works fine as long as data signalling is differential. In the presence of SE0 state, single transition occurs on either Dp or Dn pad causing high inductive kick back from choke resulting in to excessive overshoot and undershoots. The electrical over stress on cascode devices leads to device degradation resulting in to violation of USB2 output driver impedance spec of 45  +/-5%. This in turn increases defects per million count over time. To mitigate this reliability issue EOS protection circuit is proposed. This circuit is designed in Intel-22nm process and evaluated by computer simulations across all PVT conditions. Proposed EOS protection circuit reduces respective overshoot and undershoot of 4.2V and -0.6V to 3.7V and -0.34V. For the growing EOS concern of deep submicron devices in 14nm, 10nm and onward technologies, this invention becomes an ideal